Market Overview: The Design Software & IP Layer
Chip design requires two categories of tools and inputs:
1. Electronic Design Automation (EDA) Software
EDA Workflow:
- Specification & Behavior: Designer defines chip function, performance targets.
- RTL Design (Register-Transfer Level): Using hardware description languages (Verilog, SystemVerilog, VHDL).
- Simulation & Verification: Testing design behavior against requirements.
- Synthesis: Converting RTL into gate-level logic.
- Physical Design (P&R): Placing transistors and routing connections on die.
- Verification & Sign-Off: Final electrical and manufacturing checks.
Each step uses specialized EDA tools from major vendors.
2. Semiconductor IP (Intellectual Property) Cores
Pre-designed and verified functional blocks that designers license and integrate into their chips:
- CPU Cores: Arm Cortex, ARM Neoverse (dominant); RISC-V (open-source, emerging)
- GPU Cores: Arm Mali, Imagination PowerVR
- Memory Macros: Memory compilers from foundries (TSMC, Samsung) and specialist IP vendors
- I/O & Analog Blocks: SerDes, PLL, power management IP
- Interconnect IP: Arm CoreLink, others
Economics: Using IP cores is vastly cheaper and faster than designing from scratch. A smartphone SoC (system-on-chip) using Arm CPU + GPU cores takes 18–24 months; designing custom CPU/GPU from scratch would take 4–5 years and cost 10x more.
Market Share & Competitive Landscape
EDA Market (2025–2026)
| Vendor | Market Share | Strengths | Notes |
|---|---|---|---|
| Synopsys | ~35–40% | Logic design, simulation (after ANSYS merger), verification | #1 EDA vendor by revenue |
| Cadence | ~30–35% | Analog/mixed-signal, custom design, system analysis | #2 EDA vendor; strong in analog |
| Mentor Graphics (Siemens) | ~15% | PCB design, system simulation, automotive | Smaller in pure silicon EDA |
| Ansys (now Synopsys) | ~10% | Physics simulation, multiphysics | Merged with Synopsys July 2025 |
| Others | ~10% | Academic tools, niche players | Incisive (Siemens), others |
Semiconductor IP Market (2025–2026)
| Provider | Product Category | Market Position | Notes |
|---|---|---|---|
| Arm Holdings | CPU cores (Cortex, Neoverse), GPU (Mali), interconnect | 99% in mobile SoCs; 80%+ in embedded; 10%+ in data center | Dominant; royalty-based model |
| Imagination Technologies | GPU cores (PowerVR), interconnect | ~3–5% in mobile/embedded GPUs | Smaller but strong in niche |
| RISC-V (Open-Source) | CPU cores (open instruction set) | <1% current deployment; growing 20%+ YoY | Emerging threat to Arm; vendor-independent |
| NVIDIA | GPU designs (proprietary) | Dominant in data center GPUs | Not a traditional IP licensor; ships in own products |
| Memory IP Specialists | Memory compilers, I/O macros | Fragmented; foundries (TSMC, Samsung) provide memory IP | Specialized vendors (Lanner, etc.) provide alternative blocks |
Key Company Profiles
Detailed profiles for strategically significant EDA and IP providers:
- Synopsys — EDA #1; ANSYS acquisition (completed July 2025) consolidates design+simulation; CEO Sassine Ghazi; export controls dimension
- Cadence Design Systems — EDA #2; analog/mixed-signal strength; CEO Anirudh Devgan; joined Lam Research board
- Arm Holdings — IP licensing; CPU cores (Cortex, Neoverse), GPU (Mali); CEO Rene Haas; IPO September 2023; SoftBank ownership; royalty model; customer concentration
Strategic Insights: EDA Export Controls & Geopolitics
US Export Controls on EDA Tools to China
Background: EDA software (Synopsys, Cadence tools) is critical to advanced chip design. Restricting Chinese designers’ access to these tools constrains China’s ability to design advanced chips independently.
Current Restrictions (As of April 2026):
- Synopsys tools have been restricted from export to certain Chinese entities and government agencies.
- Cadence tools also face restrictions.
- The restrictions target specific Chinese companies (e.g., Huawei, SMIC, military contractors) rather than blanket bans.
Impact:
- Chinese fabs (SMIC, YMTC) rely on reverse-engineered or older-generation EDA tools.
- This slows Chinese chip design cycles and innovation.
- However, Chinese companies are developing indigenous EDA alternatives (e.g., Xpeedic tools), though not yet at Synopsys/Cadence quality levels.
Strategic Importance: ⚑ EDA tool export controls are as critical as fab equipment or advanced materials in controlling adversary chip advancement. A comprehensive EDA embargo would halt advanced Chinese chip design.
Market Trends & Future Directions
AI-Driven Chip Design
EDA vendors are investing heavily in AI/machine learning to accelerate design workflows:
- Synopsys & Cadence: Both developing AI tools for placement optimization, power analysis, and design space exploration.
- Timeline: AI-driven tools expected to reduce design time by 20–30% by 2027–2028.
Arm CPU Core Diversification
While Arm dominates, alternative instruction set architectures are emerging:
- RISC-V: Open-source, vendor-neutral architecture gaining traction in IoT, embedded, and data center.
- China’s “Loongson” ISA: Chinese alternative to Arm; limited global adoption.
- Impact on Arm: Arm’s dominance remains strong, but RISC-V could capture 5–10% of data center market by 2030.
System-on-Chip (SoC) Complexity
Modern SoCs integrate CPU, GPU, memory, analog circuits, and specialty blocks. This complexity drives demand for:
- Integrated EDA platforms (Synopsys + ANSYS offering combined EDA+simulation).
- Pre-designed multi-core IP packages (reducing design cycles).
Risks & Uncertainties
EDA Duopoly & Pricing Risk
Synopsys and Cadence command ~70% market share. This duopoly:
- Gives vendors pricing power → EDA tool costs rising faster than chip design productivity.
- Limits competition and innovation in niche areas (e.g., analog/mixed-signal design).
- Creates dependency risk for large chip companies (TSMC, Intel, Samsung).
Potential Solution: Open-source EDA tools (e.g., OpenROAD, other DARPA-funded initiatives) are emerging but not yet competitive at advanced nodes.
Arm IP Royalty Model
Arm licenses IP cores and collects royalties (typically 1–4% of chip revenue, depending on complexity):
- Growing data center adoption increases Arm’s royalty stream.
- However, this model creates margin pressure for chip companies and incentivizes RISC-V alternatives.
Export Control Escalation
If US-China relations deteriorate, comprehensive EDA tool export bans could:
- Cripple Chinese chip design innovation.
- Create reciprocal retaliatory actions (e.g., Chinese companies restricting IP licensing).
- Force development of indigenous EDA alternatives (bad for US vendors, but eventual outcome uncertain).